Merged memory logic (MML) integrated circuits are conventionally used in lightweight or compact systems to provide high performance and reduced power consumption. A typical MML integrated circuit includes memory, e.g., a dynamic random access memory (DRAM) or a static random access memory (SRAM), along with logic appropriate to control the memory, combined on a single chip. Typically, the logic controls the writing and reading of data in the memory.
FIG. 1 is a block diagram of a conventional semiconductor memory integrated circuit 101. The integrated circuit 101 includes an input terminal clock buffer 111, an input buffer 121, an output terminal clock buffer 141, an output buffer 131 and a memory 151. The input terminal clock buffer 111 generates an internal clock signal PCLK in response to an external clock signal CLK. The input buffer 121 transmits received data DI1 to the memory 151 in response to the internal clock signal PCLK. The input terminal clock buffer 111 includes an internal clock generator 113 for generating the internal clock signal PCLK from the external clock signal CLK, the internal clock signal being delayed by an interval introduced by a delay 115.
Similarly, the output terminal clock buffer 141 generates an output clock signal DLKDO in response to the clock signal CLK. The output buffer 131 produces data DQ2 from data DQ1 received from the memory 151 in response to the output clock signal DLKDO. The output terminal clock buffer 141 includes an output control clock generator 143 for converting the clock signal CLK to the output clock signal DLKDO, delayed by an interval introduced by a delay 145.
Variations in process conditions can cause variations in the timing characteristics, e.g., setup and hold times, of memory integrated circuits. Compensation for these variations may require changes to the masks of the delays or other structures in the memory integrated circuit, often resulting in production delays, increased cost, and the like.